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Class Number: 371
Class Title: ERROR DETECTION/CORRECTION AND FAULT DETECTION/RECOVERY
Subclass Subclass
Number Title
1 SKEW DETECTION/CORRECTION
2.1 DATA FORMATTING TO IMPROVE ERROR DETECTION/CORRECTION
CAPABILITY
2.2 .Memory access (e.g., address permutation)
3 TESTING OF ERROR-CHECK SYSTEM
4 ERROR/FAULT ANTICIPATION
5.1 ERROR COUNT OR RATE
5.2 .Pseudo-error rate
5.3 .Up-down counter
5.4 .Synchronization control
5.5 .Shutdown or establishing system parameter (e.g.,
transmission rate)
6 DATA PULSE EVALUATION/BIT DECISION
7 APPARATUS FAULT RECOVERY
8.1 .Replacement with spare device or system
8.2 ..Transmission facility or channel
9.1 ..Standby data processor or computer
10.1 ..Memory
10.2 ...Spare location, portion or segment
10.3 ....Spare row or column
11.1 .Reconfiguration
11.2 ..Transmission facility
11.3 ..Data processor or computer
12 .Program restart/operation retry
13 ..Storage readout
14 .Fail-safe shutdown
15.1 DIAGNOSTIC TESTING
16.1 .Programmable processor testing
16.2 ..Emulator device
16.3 ..Watchdog timer (e.g., time-out)
16.4 ..Processor within diverse device (microwave, photocopier)
16.5 ..Error or fault, logging or tracking
17 ..Operator controlled
18 ..Dedicated maintenance subsystem
19 .Testing of computer programs
20.1 .Transmission facility testing
20.2 ..For channel having repeater
20.3 ..By tone signal
20.4 ..Test pattern with comparison
20.5 ...Loop-back
20.6 ..Loop or ring configuration
21.1 .Memory
21.2 ..Read-in with read-out and compare
21.3 ...Special test patterns (e.g., checkerboard, walking
ones)
21.4 ..Electrical parameters (e.g., threshold voltage)
21.5 ..Arithmetic function of memory contents
21.6 ..Error mapping or logging
22.1 .Digital logic testing
22.2 ..Programmable logic array (PLA) testing
22.3 ..Scan path testing (LSSD)
22.4 ..Signature analysiss
22.5 ..Built-in testing circuit (BILBO)
22.6 ..Structural (in-circuit test)
23 .Fault simulation/circuit simulation
24 .Device response compared to input pattern
25.1 .Device response compared to expected fault-free response
26 .Device response compared to fault dictionary/truth table
27 .Including test pattern generator
28 .Determination of marginal operation limits
29.1 .Error or fault, logging or tracking (e.g., status
display)
29.5 .Bus fault testing
30 DIGITAL DATA ERROR CORRECTION
31 .Substitution of previous valid data
32 .Request for retransmission
33 ..Retransmission if no ACK returned
34 ..Feedback to transmitter for comparison
35 ..Including forward error correction capability
37.1 .Block code
37.2 ..Double error correcting with single error correcting
code
37.3 ..Error correction during refresh cycle
37.4 ..Double encoding codes (e.g., product, concatenated)
37.5 ...Cross-interleave reed-solomon code (CIRC)
37.6 ..Parallel generation of check bits
37.7 ..Error correcting code with additional error detection
code (e.g., cyclic redundancy character, parity)
37.8 ..Look-up table encoding or decoding
37.9 ..Threshold decoding (e.g., majority logic)
38.1 ..Random and burst error correction
39.1 ..Burst error correction
40.1 ..Memory access
40.2 ...Error correct and restore
40.3 ...Error pointer
40.4 ...Check bits stored in separable area of memory
41 ..Adaptive error-correcting capability
42 ..Synchronization
43 .Convolutional code
44 ..Random and burst errors
45 ..Burst errors
46 ..Synchronization
36 .Majority decision/voter circuit
47.1 ERROR DETECTION FOR SYNCHRONIZATION CONTROL
48 ERROR/FAULT DETECTION TECHNIQUES
49.1 .Parity bit
49.2 ..Parity generator or checker circuit detail
49.3 ..Even and odd parity
49.4 ..Parity prediction
50.1 ..Plural dimension parity check
51.1 ..Storage accessing (e.g., address parity check)
52 .Constant-ratio code (m/n)
53 .Check character
54 ..Modulo-n residue check character
55 .Code constraint monitored
56 ..Multilevel coding (n>2)
57.1 .Forbidden combination or improper condition
57.2 ..Specified digital signal or pulse count
59 ..Two key-down detector
60 ..Improper operation sequencee
61 ..Data timing/clocking
62 ..Time delay/interval monitored
63 ..Two-rail logic
64 ..Noise level
65 ..Missing-bit/drop-out detection
66 ..Power failure
67.1 .Comparison of data
68.1 ..Plural parallel devices of channels
68.2 ...Transmission facility
68.3 ...Data processor or computer
69.1 ..Sequential repetition
70 ...True and complement data
71 ..Device output compared to input
72 MISCELLANEOUS