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Class Number: 437
Class Title: SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS
Subclass Subclass
Number Title
1 MAKING DEVICE HAVING ORGANIC SEMICONDUCTOR COMPONENT
2 MAKING DEVICE RESPONSIVE TO RADIATION
3 .Radiation detectors, e.g., infrared, etc.
4 .Composed of polycrystalline material
5 .Having semiconductor compound
6 MAKING THYRISTOR, E.G., DIAC, TRIAC, ETC.
7 INCLUDING CONTROL RESPONSIVE TO SENSED CONDITION
8 INCLUDING TESTING OR MEASURING
9 INCLUDING APPLICATION OF VIBRATORY FORCE
10 INCLUDING GETTERING
11 .By ion implanting or irradiating
12 .By layers which are coated, contacted, or diffused
13 .By vapor phase surface reaction
14 THERMOMIGRATION
15 INCLUDING FORMING A SEMICONDUCTOR JUNCTION
16 .Using energy beam to introduce dopant or modify dopant
distribution
17 ..Neutron, gamma ray or electron beam
18 ..Ionized molecules
19 ..Coherent light beam
20 ..Ion beam implantation
21 ...Of semiconductor on insulating substrate
22 ...Of semiconductor compound
23 ....Light emitting diode (LED)
24 ...Providing nondopant ion including proton
25 ...Providing auxiliary heating
26 ...Forming buried region
27 ...Including multiple implantations of same region
28 ....Through insulating layer
29 .....Forming field effect transistor (FET) type device
30 ....Using same conductivity type dopant
31 ....Forming bipolar transistor (NPN/PNP)
32 .....Lateral bipolar transistor
33 .....Having dielectric isolation
34 ....Forming complementary MOS (metal oxide semiconductor)
35 ...Using oblique beam
36 ...Using shadow mask
37 ...Having projected range less than thickness of dielectrics on
substrate
38 ...Into shaped or grooved semiconductor substrate
39 ...Involving Schottky contact formation
40 ...Forming pair of device regions separated by gate structure,
i.e., FET
41 ....Self-aligned
42 .....Gate structure constructed of diverse dielectrics
43 .....Gate surrounded by dielectric layer, e.g., floating gate,
etc.
44 .....Adjusting channel dimension
45 .....Active step for controlling threshold voltage
46 ...Into polycrystalline or polyamorphous regions
47 ...Integrating active with passive devices
48 ...Forming plural active devices in grid/arrays, e.g.,,
RAMS/ROMS, etc.
49 ....Having multi-level electrodes
50 ...Forming electrodes in laterally spaced relationships
51 .Making assemblies of plural individual devices having community
feature, e.g., integrated circuit, electrical connection, etc.
52 ..Memory devices
53 ..Charge coupled devices (CCD)
54 ..Diverse types
55 ...Integrated injection logic (I2L) circuits
56 ...Plural field effect transistors (CMOS)
57 ....Complementary metal oxide having diverse conductivity source
and drain regions
58 ....Having like conductivity source and drain regions
59 ...Including field effect transistor
60 ...Including passive device
61 .Including isolation step
62 ..By forming total dielectric isolation
63 ..By forming vertical isolation combining dielectric and PN
junction
64 ..Using vertical dielectric (air-gap/insulator) and horizontal
PN junction
65 ...Grooved air-gap only
66 ....V groove
67 ...Grooved and refilled with insulator
68 ....V groove
69 ...Recessed oxide by localized oxidation
70 ....Preliminary formation of guard ring
71 ....Preliminary anodizing
72 ....Preliminary etching of groove
73 .....Using overhanging oxidation mask and pretreatment of
recessed walls
74 ..Isolation by PN junction only
75 ...By diffusion from upper surface only
76 ...By up-diffusion from substrate region and down diffusion into
upper surface layer
77 ....Substrate and epitaxial regions of same conductivity type,
i.e., P or N
78 ...By etching and refilling with semiconductor material having
diverse conductivity
79 ...Using polycrystalline region
80 .Shadow masking
81 .Doping during fluid growth of semiconductor material on
substrate
82 ..Including heat to anneal
83 ..Growing single crystal on amorphous substrate
84 ..Growing single crystal on single crystal insulator (SOS)
85 ..Including purifying stage during growth
86 ..Using transitory substrate
87 ..Using inert atmosphere
88 ..Using catalyst to alter growth process
89 ..Growth through opening
90 ...Forming recess in substrate and refilling
91 ....By liquid phase epitaxy
92 ...By liquid phase epitaxy
93 ..Specified crystal orientation other than (100) or (111)
planes
94 ..Introducing minority carrier life time reducing dopant during
growth, i.e., deep level dopant Au(Gold), Cr(Chromium),,
Fe(Iron), Ni(Nickel), etc.
95 ..Autodoping control
96 ...Compound formed from Group III and Group V elements
97 ..Forming buried regions with outdiffusion control
98 ...Plural dopants simultaneously outdiffusioned
99 ..Growing mono and polycrystalline regions simultaneously
100 ..Growing silicon carbide (SiC)
101 ..Growing amorphous semiconductor material
102 ..Source and substrate in close-space relationship
103 ...Group IV elements
104 ...Compound formed from Group III and Group V elements
105 ..Vacuum growing using molecular beam, i.e., vacuum deposition
106 ...Group IV elements
107 ...Compound formed from Group III and Group V elements
108 ..Growing single layer in multi-steps
109 ...Polycrystalline layers
110 ...Using modulated dopants or materials, e.g., superlattice,
etc.
111 ...Using preliminary or intermediate metal layer
112 ...Growing by varying rates
113 ..Using electric current, e.g., Peltier effect, glow discharge
etc.
114 ..Using seed in liquid phase
115 ...Pulling from melt
116 ....And diffusing
117 ..Liquid and vapor phase epitaxy in sequence
118 ..Involving capillary action
119 ..Sliding liquid phase epitaxy
120 ...Modifying melt composition
121 ...Controlling volume or thickness of growth
122 ...Preliminary dissolving substrate surface
123 ...With nonlinear slide movement
124 ...One melt simulataneously contacting plural substrates
125 ..Tipping liquid phase epitaxy
126 ..Heteroepitaxy
127 ...Multi-color light emitting diode (LED)
128 ...Graded composition
129 ...Forming laser
130 ...By liquid phase epitaxy
131 ...Si(Silicon) on Ge(Germanium) or Ge(Germanium) on Si(Silicon)
132 ...Either Si(Silicon) or Ge(Germanium) layered with or on
compound formed from Group III and Group V elements
133 ...Compound formed from Group III and Group V elements on
diverse Group III and Group V including substituted Group III
and Group V compounds
134 .By fusing dopant with substrate, e.g., alloying, etc.
135 ..Using flux
136 ..Passing electric current through material
137 ..With application of pressure to material during fusing
138 ..Including plural controlled heating or cooling steps
139 ..Including diffusion after fusion step
140 ..Including additional material to improve wettability or flow
characteristics
141 .Diffusing a dopant
142 ..To control carrier lifetime, i.e., deep level dopant Au(Gold),
Cr(Chromium), Fe(Iron), Ni(Nickel), etc.
143 ..Al(Aluminum) dopant
144 ..Li(Lithium) dopantt
145 ..Including nonuniform heating
146 ..To solid state solubility concentration
147 ..Using multiple layered mask
148 ...Having plural predetermined openings in master mask
149 ..Forming partially overlapping regions
150 ..Plural dopants in same region, e.g., through same mask
opening, etc.
151 ...Simultaneously
152 ..Plural dopants simultaneously in plural regions
153 ..Single dopant forming plural diverse regions
154 ...Forming regions of different concentrations or of different
depths
155 ..Using metal mask
156 ..Outwardly
157 ..Laterally under mask
158 ..Edge diffusion by using edge portion of structure other than
masking layer to mask
159 ..From melt
160 ..From solid dopant source in contact with substrate
161 ...Using capping layer over dopant source to prevent out
diffusion of dopant
162 ...Polycrystalline semiconductor source
163 ...Organic source
164 ...Glassy source or doped oxide
165 ..From vapor phase
166 ...In plural stages
167 ...Zn(Zinc) dopant
168 ...Solid source in operative relation with semiconductor
material
169 ....In capsule type enclosure
170 DIRECTLY APPLYING ELECTRICAL CURRENT
171 .And regulating temperature
172 .Altering or pulsed current
173 APPLYING CORPUSCULAR OR ELECTROMAGNETIC ENERGY
174 .To anneal
175 FORMING SCHOTTKY CONTACT
176 .On semiconductor compound
177 ..Multi-layer elctrode
178 .Using Platinum Group silicide, i.e., silicide of Pt(Platinum),
Pd(Palladium), Rh(Rhodium), Ru(Ruthenium),Ir(Iridium),
Os(Osmium)
179 .Using metal, i.e., Pt(Platinum), (Pd(Palladum), Rh(Rhodium,
(Ru(Rutenium), Ir(Iridium, Os(Osmium), Au(Gold), Ag(Silver
180 MAKING OR ATTACHING ELECTRODE ON OR TO SEMICONDUCTOR, OR
SECURING COMPLETED SEMICONDUCTOR TO MOUNTING OR HOUSING
181 .Forming transparent electrode
182 .Forming beam electrode
183 .Forming bump electrode
184 .Electrode formed on substrate composed of elements of Group III
and Group V semiconductor compound
185 .Electrode formed on substrate composed of elements of Group II
and Group VI semiconductor compound
186 .Single polycrystalline electrode layer on substrate
187 .Single metal layered electrode on substrate
188 ..Subsequently fusing, e.g., alloying, sintering, etc.
189 .Forming plural layered electrode
190 ..Including central layer acting as barrier between outer
layerss
191 ..Of polysilicon only
192 ..Includng refractory metal layer of Ti(Titanium),
Zr(Zirconium), Hf(Hafnium), V(Vanadium), Nb(Niobium),
Ta(Tantalum), Cr(Chromium), Mo(Molybdenum), W(Tungsten)
193 ..Including polycrystalline silicon layer
194 ..Including Al(Aluminum) layer
195 ..Including layer separated by insulator
196 .Forming electrode of alloy or electrode of a compound of
Si(Silicon)
197 ..Al(Aluminum) alloy
198 ...Including Cu(Copper)
199 ...Including Si(Silicon)
200 ..Silicide of Ti(Titanium), Zr(Zirconium), Hf(Hafnium),
V(Vanadium), Nb(Niobium), Ta(Tantalum), Cr(Chromium),
Mo(Molybdenum), W(Tungsten)
201 ..Of plantinum metal group Ru(Ruthenium), Rh(Rhodium),
Pd(Palladium), Os(Osmium, Ir(Iridium), Pt(Platinum)
202 ..By fusing metal with semiconductor (alloying)
203 .Depositing electrode in preformed recess in substrate
204 .Including positioning of point contact
205 .Making plural devices
206 ..Using strip lead frame
207 ...And encapsulating
208 ..Stacked array, e.g., rectifier, etc.
209 .Securing completed semiconductor to mounting, housing or
external lead
210 ..Including contaminant removal
211 ..Utilizing potting or encapsulating material only to surround
leads and device to maintain position, i.e., without housing
212 ...Including application of pressure
213 ...Glass material
214 ..Utilizing header (molding surface means)
215 ..Insulating housing
216 ...Including application of pressure
217 ...And lead frame
218 ...Ceramic housing
219 ...Including encapsulating
220 ..Lead frame
221 ..Metallic housing
222 ...Including applicaion of pressure
223 ...Including glass support base
224 ...Including encapsulating
225 INCLUDING COATING OR MATERIAL REMOVAL, E.G., ETCHING, GRINDING,
ETC.
226 .Substrate dicing
227 ..With a perfecting coating
228 .Coating and etching
229 .Of radiation resist layer
230 .By immersion metal plating from solution, i.e., electroless
plating
231 .By spinning
232 .Elemental Se(Selenium) substrate or coating
233 .Of polycrystalline semiconductor material on substrate
234 ..Semiconductor compound or mixed semiconductor material
235 .Of a dielectric or insulatve material
236 ..Containing Group III atom
237 ...By reacting with substrate
238 ..Monoxide or dioxide of Ge(Germanium) or Si(Silicon))
239 ...By reacting with substrate
240 ...Doped with impurities
241 ..Si(Silicon) and N(Nitrogen)
242 ...By chemical reaction with substrate
243 ..Directly on semiconductor substrate
244 ...By chemical conversion of substrate
245 .Comprising metal layer
246 ..On metal
247 TEMPERATURE TREATMENT MODIFYING PROPERTIES OF SEMICONDUCTOR,
E.G., ANNEALING, SINTERING, ETC.
248 .Heating and cooling
249 INCLUDING SHAPING
250 MISCELLANEOUS
* ******************************
* CROSS-REFERENCE ART COLLECTIONS
* ******************************
900 UTILIZING PROCESS EQUIVALENTS OR OPTIONS
901 MAKING PRESSURE SENSITIVE DEVICE
902 MAKING DEVICE HAVING HEAT SINK
903 MAKING THERMOPILE
904 MAKING DIODE
905 .Light emmitting diode
906 ..Mounting and contact
907 LASER PROCESSING OF FIELD EFFECT TRANSISTOR (FET)
908 LASER PROCESSING OF TRANSISTOR
909 MAKING TRANSISTOR ONLY
910 MAKING JOSEPHSON JUNCTION DEVICE
911 MAKING JUNCTION-FIELD EFFECT TRANSISTOR (J-FET) OR STATIC
INDUCTION THYRSISTOR (SIT) DEVICE
912 MAKING METAL SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MESFET)
DEVICE ONLY
913 MAKING METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR
(MOSFET) DEVICE
914 MAKING NON-EPITAXIAL DEVICE
915 MAKING VERTICALLY STACKED DEVICES (3-DIMENSIONAL STRUCTURE)
916 MAKING PHOTOCATHODE OR VIDICON
917 MAKING LATERAL TRANSISTOR
918 MAKING RESISTOR
919 MAKING CAPACITOR
920 MAKING SILICON-OXIDE-NITRIDE-OXIDE ON SILICON (SONOS) DEVICE
921 MAKING STRAIN GAGE
922 MAKING FUSE OR FUSABLE DEVICE
923 WITH REPAIR OR RECOVERY OF DEVICE
924 HAVING SUBSTRATE OR MASK ALIGNING FEATURE
925 SUBSTRATE SUPPORT OR CAPSULE CONSTRUCTION
926 CONTINUOUS PROCESSING
927 FORMING HOLLOW BODIES AND ENCLOSED CAVITIES
928 ENERGY BEAM TREATING RADIATION RESIST ON SEMICONDUCTOR
929 RADIATION ENHANCED DIFFUSION (R.E.D.)
930 ION BEAM SOURCE AND GENERATION
931 IMPLANTATION THROUGH MASK
932 RECOIL IMPLANTATION
933 DUAL SPECIES IMPLANTATION OF SEMICONDUCTOR
934 DOPANT ACTIVATION PROCESS
935 BEAM WRITING OF PATTERNS
936 BEAM PROCESSING OF COMPOUND SEMICONDUCTOR DEVICE
937 HYDROGEN PLASMA TREATMENT OF SEMICONDUCTOR DEVICE
938 MAKING RADIATION RESISTANT DEVICEE
939 DEFECT CONTROL OF SEMICONDUCTOR WAFER (PRETREATMENT)
940 SELECTIVE OXIDATION OF ION AMORPHOUSIZED LAYERS
941 CONTROLLING CHARGING STATE AT SEMICONDUCTOR-INSULATOR INTERFACE
942 INCOHERENT LIGHT PROCESSING
943 THERMALLY ASSISTED BEAM PROCESSING
944 UTILIZING LIFT OFF
945 STOICHIOMETRIC CONTROL OF HOST SUBSTRATE COMPOSITION
946 SUBSTRATE SURFACE PREPARATION
947 FORMING TAPERED EDGES ON SUBSTRATE OR ADJACENT LAYERS
948 MOVABLE MASK
949 CONTROLLED ATMOSPHERE
950 SHALLOW DIFFUSION
951 AMPHOTERIC DOPING
952 CONTROLLING DIFFUSION PROFILE BY OXIDATION
953 DIFFUSION OF OVERLAPPING REGIONS (COMPENSATION)
954 VERTICAL DIFFUSION THROUGH A LAYER
955 NONSELECTIVE DIFFUSION
956 DISPLACING P-N JUNCTION
957 ELECTROMIGRATION
958 SHAPED JUNCTION FORMATION
959 USING NONSTANDARD DOPANT
960 WASHED EMITTER PROCESS
961 EMITTER DIP PREVENTION (OR UTILIZATION)
962 UTILIZING SPECIAL MASKS (CARBON, ETC.)
963 LOCALIZED HEATING CONTROL DURING FLUID GROWTH
964 FLUID GROWTH INVOLVING VAPOR-LIQUID-SOLID STAGES
965 FLUID GROWTH OF COMPOUNDS COMPOSED OF GROUPS II, IV, OR VI
ELEMENTS
966 FORMING THIN SHEETS
967 PRODUCING POLYCRYSTALLINE SEMICONDUCTOR MATERIAL
968 SELECTIVE OXIDATION OF POLYCRYSTALLINE LAYER
969 FORMING GRADED ENERGY GAP LAYERS
970 DIFFERENTIAL CRYSTAL GROWTH
971 FLUID GROWTH DOPING CONTROL
972 UTILIZING MELT-BACK
973 SOLID PHASE EPITAXIAL GROWTH
974 THINNING OR REMOVAL OF SUBSTRATE
975 DIFFUSION ALONG GRAIN BOUNDARIES
976 CONTROLLING LATTICE STRAIN
977 UTILIZING ROUGHENED SURFACE
978 UTILIZING MULTIPLE DIELECTRIC LAYERS
979 UTILIZING THICK-THIN OXIDE FORMATION
980 FORMING POLYCRYSTALLINE SEMICONDUCTOR PASSIVATION
981 PRODUCING TAPERED ETCHING
982 REFLOW OF INSULATOR
983 OXIDATION OF GATE OR GATE CONTACT LAYER
984 SELF-ALIGNING FEATURE
985 DIFFERENTIAL OXIDATION AND ETCHING
986 DIFFUSING LATERALLY AND ETCHING
987 DIFFUSING DOPANTS IN COMPOUND SEMICONDUCTOR